Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
In conventional flipchip type packages, a semiconductor die is mounted to a package substrate with the active side of the die facing the substrate. Conventionally, the interconnection of the circuitry in the die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding complementary array of interconnect pads, often referred to as capture pads on the substrate.
The areal density of electronic features on integrated circuits has increased enormously, and semiconductor die having a greater density of circuit features also may have a greater density of sites for interconnection with the package substrate.
The package is connected to underlying circuitry, such as a printed circuit board or motherboard, by way of second level interconnects between the package and the underlying circuit. The second level interconnects have a greater pitch than the flipchip interconnects, and so the routing on the substrate conventionally fans out. Significant technological advances have enabled construction of fine lines and spaces. The space between adjacent pads limits the number of traces than can escape from the more inward capture pads in the array. The fan-out routing between the capture pads beneath the die and external pins of the package is conventionally formed on multiple metal layers within the package substrate. For a complex interconnect array, substrates having multiple layers can be required to achieve routing between the die pads and second level interconnects on the package.
Multiple layer substrates are expensive and, in conventional flipchip constructs, the substrate alone typically accounts for more than half the package cost. The high cost of multilayer substrates has been a factor in limiting proliferation of flipchip technology in mainstream products. The escape routing pattern typically introduces additional electrical parasitics because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.
The flipchip interconnection can be made by using a melting process to join the bumps, e.g., solder bumps, onto the mating surfaces of the corresponding capture pads, referred to as bump-on-capture pad (BOC) interconnect. Two features are evident in the BOC design: first, a comparatively large capture pad is required to mate with the bump on the die, and second, an insulating material, typically a solder mask, is required to confine the flow of solder during the interconnection process. The solder mask opening defines the contour of the melted solder at the capture pad, i.e. solder mask defined, or the solder contour may not be defined by the mask opening, i.e. non-solder mask defined. In the latter case, the solder mask opening is significantly larger than the capture pad. Since the techniques for defining solder mask openings have wide tolerance ranges for a solder mask defined bump configuration, the capture pad must be large, typically considerably larger than the design size for the mask opening, to ensure that the mask opening will be located on the mating surface of the pad. For a non-solder mask defined bump configuration, the solder mask opening must be larger than the capture pad. The width of capture pads or diameter can be as much as two to four times wider than the trace width. The larger width of the capture pads results in considerable loss of routing space on the top substrate layer. In particular, the escape routing pitch is much larger than the finest trace pitch that the substrate technology can offer. A significant number of pads must be routed on lower substrate layers by means of short stubs and vias, often beneath the footprint of the die, emanating from the pads in question.
In a typical example of a conventional solder mask defined BOC interconnection, the capture pad has a diameter about 140 μm, and the solder mask opening has a diameter about 90 μm, and the routing traces are about 25-30 μm wide. The diameter of the mating surface for attachment of the bump to the die pad, that is, the place of interface between the bump and the die pad, is defined by the solder mask opening as having a diameter about 90 μm.
Conventional BOC interconnect layouts are shown in FIGS. 1 and 2 as portions 10 and 20 of a flipchip package. The partial sectional view in FIG. 1 is taken in a plane parallel to the package substrate surface, along the line 1-1′ in FIG. 2. The partial sectional view in FIG. 2 is taken in a plane perpendicular to the package substrate surface, along the line 2-2′ in FIG. 1. Certain features are shown as if transparent, but many of the features in FIG. 1 are shown partly obscured by overlying features.
In FIGS. 1 and 2, a die attach surface of the package substrate includes a metal or layer formed on a dielectric layer over substrate 12. The metal layer is patterned to form traces or leads 13 and capture pads 14. An insulating layer or solder mask 16 covers the die attach surface of substrate 12. Solder mask 16 is usually a photo-definable material patterned by photoresist to leave the mating surfaces of capture pads 14 exposed. The interconnect bumps 15 attached to pads on the active side of semiconductor die 18 are joined to the mating surfaces of corresponding capture pads 14 on substrate 12 to form appropriate electrical interconnection between the circuitry on the die and the leads on the substrate. After the reflowed solder is cooled to establish the electrical connection, an underfill material 17 is introduced into the space between semiconductor die 18 and substrate 12 to mechanically stabilize the interconnects and protect the features between the die and substrate.
FIG. 1 shows signal escape traces 13 in the upper metal layer of substrate 12 routed from their respective capture pads 14 across the die edge location, indicated by broken line 11, and away from the die footprint. The signal traces 13 can have an escape pitch PE about 112 micrometers (μm). A 30 μm/30 μm design rule is typical for traces 13 in a configuration such as shown in FIG. 1. Traces 13 are nominally 30 μm wide and can be spaced as close together as 30 μm. The capture pads 14 are typically three times greater than the trace width, and the capture pads have a width or diameter nominally 90 μm. The openings in the solder mask are larger than the pads, having a nominal width or diameter of 135 μm.
FIGS. 1 and 2 show a non-solder mask defined solder contour. As the fusible material of the bumps on the die melt, the molten solder tends to wet the metal of the leads and capture pads and the solder tends to run out over any contiguous metal surfaces that are not masked. The solder tends to flow along the contiguous lead 13, and here the solder flow is limited by the solder mask at location 19 in FIG. 1. A non-solder mask defined solder contour at the pad is apparent in FIG. 2, in which portion 29 of bumps 15 is shown as having flowed over the sides of capture pads 14 and down to the surface of the dielectric layer of substrate 12. The non-solder mask defined contour does not limit the flow of solder over the surface and down over the sides of the capture pads and, unless there is a substantial excess of solder at the pad, the flow of solder is limited by the fact that the dielectric surface of the substrate is typically not wettable by the molten solder. A lower limit on the density of the capture pads in the arrangement shown in FIG. 1 is determined by, among other factors, the capacity of the mask forming technology to make reliable narrow mask structures and the need to provide mask structures between adjacent mask openings. A lower limit on the escape density is additionally determined by, among other factors, the need for escape lines from more centrally located capture pads to be routed between more peripherally located capture pads.
FIG. 3 shows a solder mask defined solder contour, in a sectional view similar to FIG. 2. Semiconductor die 38 is shown affixed by way of bumps 35 onto the mating surfaces of capture pads 34 formed along with traces or leads 33 by patterning a metal layer on the die attach side of a dielectric layer of substrate 32. After the reflowed solder is cooled to establish the electrical connection, an underfill material 37 is introduced into the space between die 38 and substrate 32 to mechanically stabilize the interconnects and protect the features between the die and substrate. Here, capture pads 34 are wider than in the example of FIGS. 1 and 2, and the solder mask openings are smaller than the capture pads, so that the solder mask material covers the sides and part of the mating surface of each capture pad, as shown at location 39, as well as leads 33. When bumps 35 are brought into contact with the mating surfaces of the respective capture pads 34, and then melted, solder mask material 36 restricts the flow of the molten solder, so that the shapes of the solder contours are defined by the shapes and dimensions of the mask openings over capture pads 34.